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xSPI Multiple Bus Memory Controller (xSPI-MBMC)

The industry ‘defacto standard’ memory controller for xSPI-like memories

Product page​ for

OctaBus™ NOR Flash memory devices

SLL collaborates closely with Macronix regarding memory controller and related technologies.

Macronix memory devices are supported on:

SLL is an Intel Partner Alliance member

SLL is a Microchip (Microsemi) CompanionCore Partner

SLL is Trenz Electronic’s partner

SLL’s IP supports Xilinx FPGA devices

Overview of xSPI MBMC IP support for Macronix memory devices

SLL’s xSPI Multiple Bus Memory Controller IP supports the Macronix OctaBus™ (LM/LW/UM/UW) NOR Flash device family.

Macronix OctaBus™ memories offer good performance with lower hardware and power costs.  OctaBus™ device variants offer up to 2048 Mbit of storage capacity, up to 250 MHz DDR clock speeds, with x8 data path widths, and a wide range of package options.  

SLL’s is Macronix’s official partners for memory controller IP.  SLL works closely with Macronix to ensure SLL’s memory controller is physically qualified with many Macronix memory device variants, significantly reducing your project’s risks.

SLL’s small MBMC IP enables you to easily evaluate, select and adopt the benefits of Macronix’s latest memories in your projects and products.

SLL provides world class pre-sales and post-sales technical support for Macronix and all the major memory FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice.

Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s with Macronix’s memory devices.

xSPI MBMC support for FPGA and ASIC targets

This memory controller IP has been ported to, and physically tested on, a broad range of FPGA device variants, including:

  • Most modern Intel FPGA device families, including:
    • Intel MAX 10 – Up to 200 MHz DDR
    • Cyclone IV 
    • Cyclone 10 LP – Up to 200 MHz DDR
    • Cyclone 10 GX – Up to 250 MHz DDR
    • Cyclone V
    • Cyclone V SoC
    • Arria 10 – Up to 250 MHz DDR
    • Arria 10 SoC – Up to 250 MHz DDR
    • Stratix 10 – Up to 250 MHz DDR
  • Most modern Xilinx FPGA device families, including:
    • Artix-7
    • Kintex-7
    • Virtex-7
    • Zynq 7000
    • Kintex Ultrascale+
    • Zynq Ultrascale+
    • Virtex Ultrascale+ (ideal for supporting ASIC design prototyping in FPGA)
  • Microchip (Microsemi)
    • PolarFire FPGA – Up to 250 MHz DDR

Other FPGA device families may be available on request. Please contact SLL at info@synaptic-labs.com with details about the specific currently unsupported FPGA device family that you would like to use.

This memory controller IP is also currently being ported from FPGA to standard cell ASIC at up to 250 MHz DDR with x4/x8/x16 datapath support.

xSPI MBMC Trials

To request a trial for selected FPGA device families, please visit here.

xSPI MBMC Capabilities

  • Includes tight integration with all the major FPGA vendor’s graphical system integration tools (Platform Designer, Vivado, …)  
  • Features high quality local interconnect, with support for the following interconnect protocols:
    • ARM AMBA AXI4 protocol
    • ARM AMBA APB3 protocol
    • Intel Avalon-MM protocol
    • other interconnect protocols available on request…
  • Includes internal clock-crossing circuitry between the local bus interconnect and the external memory channel to reduce circuit area and improve the performance of the customer’s design
  • Excellent memory access performance for both latency sensitive and bandwidth intensive applications:
    • The round trip time for read memory transfer requests through the memory controller has been optimized for latency sensitive applications, such as processor cores.
    • The memory controller supports long burst memory transfer requests over the memory channel to sustain high effective memory bandwidth (>90% efficiency of memory channel)
    • Note:  SLL offers a range of cache technologies to significantly increase the performance of  processor cores that do not have internal instruction and/or data caches when accessing external memories.
  • Features low circuit area and low SRAM usages, making SLL’s memory controller viable for use in resource constrained designs. 
  • Includes optional support for automatic configuration of memory devices at power on:
    • FPGA customers typically use the automatic configuration option
    • This dramatically simplifies integration of SLL’s memory controller in customer designs, enabling all firmware to be executed in place from x8 NOR Flash.  
  • Include support for manual configuration of the memory controller and any attached memory devices
    • ASIC customers typically use the manual configuration option
    • ASIC customers can prototype their designs in FPGA with manual configuration option enabled
  • Supports x4, x8 and x16 data path width in a single instantiation of SLL’s memory controller IP
  • Supports 2 or more instantiations of the memory controller IP in one project
    • Preliminary support for splitting AXI4 requests across 2 instances of the memory controller in parallel to double memory bandwidth is now available

xSPI MBMC markets, applications and use cases for NOR Flash

Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China.   Applications include commercial and industrial projects and products, such as:  Sensors, video, industrial automation, medical, transport, photonics, …   Use cases include:  eXecution in Place (XiP) of software, long burst DMA access, …

xSPI MBMC support for Macronix memory devices

SLL’s memory controller supports, and is being physically qualified with, a broad range of Macronix memory device variants:

  • Macronix OctaBus™ NOR Flash  (LM/LW/UM/UW)
    • JEDEC xSPI Profile 1.0 compliant
  • Macronix OctaMCP™

xSPI MBMC support for Macronix OctaBus™

Status of Macronix OctaBus™ device testing and qualification performed by SLL:

  • Macronix International Co., Ltd – OctaBus™:
    • Physically validated on Trenz board:
      • MX25UM512 (512 Mbit, 1.8V)
    • Physical validation in process on Trenz board:
      • MX25LM51245GXDI00  (512 Mbit, 3V)
      • MX25UM51245GXDIH0  (512 Mbit, 1.8V)
      • MX25UM51345GXDI00   (512 Mbit, 1.8V)
      • MX25UW51345GXDI00   (512 Mbit, 1.8V)
      • MX66LM1G45GXDI00     (1024 Mbit, 3V)
      • MX66UM1G45GXDI00    (1024 Mbit, 1.8V)
      • MX66UM2G45GXRI00    (2048 Mbit, 1.8V)

xSPI MBMC v3 support for Macronix OctaMCP™

Status of Macronix OctaMCP™ device testing and qualification performed by SLL:

  • Macronix International Co., Ltd – OctaMCP™:
    • Physically validated on Trenz board:
      • MX65U12A64AAXDI00   (512 Mbit OctaBus™ NOR Flash, 64 Mbit PSRAM, 1.8V)
    • Physical validation in process on Trenz board:
      • MX65L12A64AAXDI00    (512 Mbit OctaBus™ NOR Flash, 64 Mbit PSRAM, 3V)

xSPI MBMC support for Commercial-off-the-shelf (COTS) boards

SLL has the broadest range of xSPI and xSPI-like board partners in this memory controller market.  SLL has also tested our memory controller on the broadest range of COTS and proprietary boards in the market.

SLL leverages our close relationships to deliver known-working reference designs with trial copies of xSPI MBMC (that do not expire) to:  (a) reduce your project risk; and (b) get you to market faster.  SLL’s board partners include:

SLL has also run our memory controller IP on boards from other board vendors such as:

List of boards supported by xSPI MBMC

Notice to Hardware Developers using xSPI MBMC

  • Please validate your pin-mapping and PCB Layout for you selected memory devices with Synaptic Laboratories at info@synaptic-labs.com before manufacturing your first prototype to reduce risks.
  • Please email info@synaptic-labs.com for SLL’s guidance with regard to supporting specific FPGA device families.

Macronix OctaBus™ Memory Resources

Macronix OctaMCP™ Resources

  • Macronix International Co., Ltd
  • Standards
    • Macronix OctaBus™
    • JEDEC JESD251 – EXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, Version 1.0
    • JEDEC JESD216D – Serial Flash Discoverable Parameters (SFDP)
  • Application notes and other guidance:
    • Contact Macronix.
  • Data sheets
    • Contact Macronix
    • MX65L
      • MX65L12A64AAXDI00    (512 Mbit NOR Flash, 64 PSRAM, 3V)
    • MX65U
      • MX65U12A64AAXDI00   (512 Mbit NOR Flash, 64 PSRAM, 1.8V)

Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: info@synaptic-labs.com

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