SLL's embedded software innovation has been recognised by our customers and partners. Major FPGA, memory, and development board makers now officially partner with SLL. This ensures SLL IP is validated on a wide range of physical devices. SLL customers are located in most geographical regions, and include Fortune Global 500's, government agencies, and SME's from USA and Canada to China.
xSPI Multiple Bus Memory Controller (xSPI-MBMC)
The industry ‘defacto standard’ memory controller for xSPI-like memories:
JEDEC xSPI Profile 2.0 NOR Flash and PSRAM devices
SLL partners and supported JEDEC xSPI Profile 2.0 memory device vendors
SLL is Trenz Electronic’s partner
SLL’s IP supports Xilinx FPGA devices
SLL is an Infineon Associated Partner
SLL is a Microchip (Microsemi) CompanionCore Partner
xSPI MBMC product overview
SLL’s xSPI Multiple Bus Memory Controller (MBMC) IP supports provides full support for xSPI Profile 2.0 including:
- Infineon® HyperRAM™ 2.0 with HyperBus™ Interface
- Infineon® Semper™ Flash with HyperBus™ Interface
- SLL’s chip-to-chip peripheral
The low pin count (11 to 12 user I/O pins) memories offer good performance with lower hardware and power costs. Memory device variants offer up to 256 Mbit PSRAM, up to 2 Gigabit NOR Flash, up to 200 MHz DDR clock speeds, with a x8 wide data path, and {6 mm x 8 mm} and {8 mm x 8 mm} BGA24 package options.
SLL is the official partner with Infineon. SLL works closely with our partners to ensure SLL’s memory controllers are physically qualified with Infineon’s memory device variants, significantly reducing your project’s risks.
SLL’s small MBMC IP v3.2.x enables you to easily evaluate, select and adopt the benefits of the latest x8 xSPI Profile 2.0 memories in your projects and products.
SLL provides world class pre-sales and post-sales technical support for all the major memory vendors and FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice.
Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s.
xSPI MBMC support for FPGA and ASIC targets
This memory controller IP has been ported to, and physically tested on, a broad range of FPGA device variants, including:
- Most modern Intel FPGA device families, including:
- Intel MAX 10 – Up to 200 MHz DDR
- Cyclone IV
- Cyclone 10 LP – Up to 200 MHz DDR
- Cyclone 10 GX – Up to 250 MHz DDR
- Cyclone V
- Cyclone V SoC
- Arria 10 – Up to 250 MHz DDR
- Arria 10 SoC – Up to 250 MHz DDR
- Stratix 10 – Up to 250 MHz DDR
- Most modern Xilinx FPGA device families, including:
- Artix-7
- Kintex-7
- Virtex-7
- Zynq 7000
- Kintex Ultrascale+
- Zynq Ultrascale+
- Virtex Ultrascale+ (ideal for supporting ASIC design prototyping in FPGA)
- Microchip (Microsemi)
- PolarFire FPGA – Up to 250 MHz DDR
Other FPGA device families may be available on request. Please contact SLL at info@synaptic-labs.com with details about the specific currently unsupported FPGA device family that you would like to use.
This memory controller IP is also currently being ported from FPGA to standard cell ASIC at up to 250 MHz DDR with x4/x8/x16 datapath support.
xSPI MBMC Trials
To request a trial for selected FPGA device families, please visit here.
xSPI MBMC Capabilities
- Includes tight integration with all the major FPGA vendor’s graphical system integration tools (Platform Designer, Vivado, …)
- Features high quality local interconnect, with support for the following interconnect protocols:
- ARM AMBA AXI4 protocol
- ARM AMBA APB3 protocol
- Intel Avalon-MM protocol
- other interconnect protocols available on request…
- Includes internal clock-crossing circuitry between the local bus interconnect and the external memory channel to reduce circuit area and improve the performance of the customer’s design
- Excellent memory access performance for both latency sensitive and bandwidth intensive applications:
- The round trip time for read memory transfer requests through the memory controller has been optimized for latency sensitive applications, such as processor cores.
- The memory controller supports long burst memory transfer requests over the memory channel to sustain high effective memory bandwidth (>90% efficiency of memory channel)
- Note: SLL offers a range of cache technologies to significantly increase the performance of processor cores that do not have internal instruction and/or data caches when accessing external memories.
- Features low circuit area and low SRAM usages, making SLL’s memory controller viable for use in resource constrained designs.
- Includes optional support for automatic configuration of memory devices at power on:
- FPGA customers typically use the automatic configuration option
- This dramatically simplifies integration of SLL’s memory controller in customer designs, enabling all firmware to be executed in place from x8 NOR Flash.
- Include support for manual configuration of the memory controller and any attached memory devices
- ASIC customers typically use the manual configuration option
- ASIC customers can prototype their designs in FPGA with manual configuration option enabled
- Supports x4, x8 and x16 data path width in a single instantiation of SLL’s memory controller IP
- Supports 2 or more instantiations of the memory controller IP in one project
- Preliminary support for splitting AXI4 requests across 2 instances of the memory controller in parallel to double memory bandwidth is now available
xSPI MBMC markets, applications and use cases
Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China. Applications include commercial and industrial projects and products, such as: Sensors, video, industrial automation, medical, transport, photonics, … Use cases include: eXecution in Place (XiP) of software, long burst DMA access, video frame buffering, packet buffering, …
xSPI MBMC JEDEC xSPI Profile 2.0 memory devices
xSPI MBMC support for Infineon HyperRAM 2.0 with HyperBus Interface
Status of Infineon HYPERRAM 2.0 memory device testing and qualification performed by SLL:
- Infineon Technologies AG – HYPERRAM 2.0 with HyperBus Interface
- Physically validated:
- S27KS0642GABHI02 ES / 7KS0642GAHIO2 ES ( 64 Mbit, 1.8V)
- S70KS1282GABHI02 ES / 7KS1282GAHV02 ES (128 Mbit, 1.8V)
- Physically validated on Trenz board:
- S70KS1282GABHV020 (128 Mbit, 1.8V)
- Physical validation in process on Trenz board:
- S70KL1282GABHV020 (128 Mbit, 3V)
- Validated in simulator:
- Pending..
- Physically validated:
xSPI MBMC support for Infineon SemperFlash with HyperBus Interface (HyperFlash 2.0)
Status of Infineon SemperFlash memory device testing and qualification performed by SLL:
- Infineon Technologies AG – Semper Flash with HyperBus Interface (HyperFlash 2.0)
- Physically validated:
- S26HS512TGABHI00 / 26HS512TAI00 (512 Megabit, 1.8V)
- Physical validation in process
- S26HL512TFPBHI01 / 26HL512TPIO1 (512 Megabit 3.0V)
- Physical validation in process on Trenz board:
- S26HL512TFPBHM010 (512 Megabit, 3V)
- S26HL01GTFPBHI030 (1 Gigabit, 3V)
- S26HS01GTGABHV030 (1 Gigabit, 1.8V)
- Physical qualification available on customer demand
- S26HS01GT (1 Gigabit, 1.8V)
- S26HL01GT (1 Gigabit, 3.0V)
- Physically validated:
xSPI MBMC v3 support for Winbond HyperRAM 2.0
Status of Winbond HyperRAM memory device testing and qualification performed by SLL:
- Winbond – HyperRAM 2.0
- Physically validated:
- W957D8MFY (128 Mbit, 1.8V)
- Physical validation in process on Trenz board:
- W957D8MFY (128 Mbit, 1.8V)
- W957A8MFY (128 Mbit, 3V)
- Validated in the Simulator
- W956D8MBYA5I (64 Mbit, 1.8V)
- W956D8MBYA6I (64 Mbit, 1.8V)
- W956A8MBYA5I (64 Mbit, 3.0V)
- W956A8MBYA5I (64 Mbit, 3.0V)
- Support available on customer request:
- W957D8MFYA5I (128 Mbit, 1.8V)
- W957A8MFYA5I (128 Mbit, 3.0V)
- W957A8MFYA6I (128 Mbit, 3.0V)
- Physically validated:
xSPI MBMC support for Commercial-off-the-shelf (COTS) boards
SLL has the broadest range of xSPI and xSPI-like board partners in this memory controller market. SLL has also tested our memory controller on the broadest range of COTS and proprietary boards in the market.
SLL leverages our close relationships to deliver known-working reference designs with trial copies of xSPI MBMC (that do not expire) to: (a) reduce your project risk; and (b) get you to market faster. SLL’s board partners include:
- Trenz Electronic GmbH
- Aries Embedded GmbH
- Devboards GmbH
- Intel Corporation (Intel PSG)
- Microsemi Corporation a wholly owned subsidiary of Microchip Technology Inc. (Microsemi)
SLL has also run our memory controller IP on boards from other board vendors such as:
Notice to Hardware Developers using xSPI MBMC
- Please validate your pin-mapping and PCB Layout for you selected memory devices with Synaptic Laboratories at info@synaptic-labs.com before manufacturing your first prototype to reduce risks.
- Please email info@synaptic-labs.com for SLL’s guidance with regard to supporting specific FPGA device families.
Infineon Semper Flash with HyperBus Interface (HyperFlash 2.0) Resources
Infineon Semper NOR Flash with HyperBus interface has conformance with JEDEC xSPI Profile 2.0:
- Infineon Technologies AG
- Standards
- HyperBus™ Specification Low Signal Count, High Performance DDR Bus
- JEDEC JESD251 – EXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, Version 1.0
- JEDEC JESD216D – Serial Flash Discoverable Parameters (SFDP)
- JEDEC JESD252 – Serial Flash Reset Signaling Protocol
- Application notes and other guidance:
- Semper Access Program
- Most of the product guidance and application notes can only be accessed by enrolling in the Semper Access Program
- AN224153 – Design and Layout Guide for Semper Flash Memory
- Requires enrolment with Semper Access Program
- AN223679 – SEMPER™ Flash conformance to JEDEC xSPI Standard
- Product selector guide for Semper Flash with HyperBus interface
- Semper Access Program
- Data sheets:
- Semper NOR Flash with HyperBus Interface Datasheet Brief
- S26HS256T/S26HS512T/S26HS01GT/S26HL256T/S26HL512T/S26HL01GT, 256-Mb (32-MB)/512-MB (64-MB)/1-GB (128-MB), HS-T (1.8-V)/HL-T (3.0-V), SEMPER(R) FLASH WITH HYPERBUS(TM) INTERFACE
- S36HS128T / S36HS256T / S36HS512T / S36HL128T / S36HL256T / S36HL512T, 128-Mb (16-MB), 256-Mb (32-MB), 512-Mb (64-MB), HS-T (1.8-V), HL-T (3.0-V) Semper Secure Flash with HyperBus Interface (Summary)
- Enrol into the Semper Access Program to get access to the full data sheets for:
- S26HS
- S26HS256T ( 256 Megabit, 1.8V)
- S26HS512T ( 512 Megabit, 1.8V)
- S26HS01GT (1024 Megabit, 1.8V)
- S26HL
- S26HL256T ( 256 Megabit, 3V)
- S26HL512T ( 512 Megabit, 3V)
- S26HL01GT (1024 Megabit, 3V)
- S36HS
- S36HS128T ( 128 Megabit, 1.8V) – Secure
- S36HS256T ( 256 Megabit, 1.8V) – Secure
- S36HS512T ( 512 Megabit, 1.8V) – Secure
- S36HL
- S36HL128T ( 128 Megabit, 3V) – Secure
- S36HL256T ( 256 Megabit, 3V) – Secure
- S36HL512T ( 512 Megabit, 1.8V) – Secure
- S26HS
Winbond HyperRAM 2.0 Resources
- Winbond
- Standards
- HyperBus™ Specification Low Signal Count, High Performance DDR Bus
- JEDEC JESD251 – EXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, Version 1.0
- JEDEC JESD216D – Serial Flash Discoverable Parameters (SFDP)
- JEDEC JESD252 – Serial Flash Reset Signaling Protocol
- Application notes and other guidance:
- Semper Access Program
- Most of the product guidance and application notes can only be accessed by enrolling in the Semper Access Program
- AN224153 – Design and Layout Guide for Semper Flash Memory
- Requires enrolment with Semper Access Program
- Semper Access Program
- Data sheets / product pages
Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: info@synaptic-labs.com
