Why throw aside the world's massive investment in the US NIST DES cipher when you can efficiently upgrade it in software? Drawing from our experience with the design of the VEST hardware cipher and our exposure to smart cards Synaptic is completing the specifications of a family of software-efficient modes-of-operation for DES.

PQSDES was purpose built to enable Synaptic Labs' key exchange technologies and a range of Lamport-Diffie-Merkle digital signatures to run efficiently on area constrained hardware devices that have a 8-bit or larger CPU and a hardware dedicated DES coprocessor. The DES operations have been optimised for compatibility with high-level cryptographic libraries present in smart cards (that prevent the use of weak DES keys) and for DES implementations that have high key schedule costs.

The DES cipher is smaller and more efficient (bits per second / gates) in highly constrained environments than the AES cipher. In area constrained applications that have already have a small micro controller the addition of a 3k gate DES coprocessor and PQSDES software enables the full suite of cryptographic operations including: key exchanges, 100 year secure single pass data privacy with message checking, collision resistant hashes and digital signatures. PQSDES with hardware DES acceleration is anticipated to achieve less power consumption than than equivalently rated operations performed using AES or SHA purely in software.  For these reasons PQSDES is ideal for ambient intelligence applications and for the first time it comprehensively removes the barrier to achieving strong feature-rich security.

PQSDES has been optimised for the very wide range of smart cards currently in production that already have hardware DES support. PQSDES in smart cards is ideal because most modern smart cards offer a processing environment that has been hardened against viruses, Trojans and side-channel attacks.  This makes PQSDES on smart cards the perfect companion to secure business desktop computing.

In desktop environments, PQSDES has been optimised to call DES without frequently changing the DES key. This important optimisation ensures that PQSDES remains efficient for secure communications between general purpose software processors without hardware acceleration.

In semiconductor applications the PQSDES cipher can be implemented with a wide range of circuit area / bandwidth trade-offs. In area constrained environments a very simple programmable finite state machine (Read, Write, XOR) can be coupled with a hardware DES module when a small micro controller is not available.  In higher performance applications PQSDES can be implemented with two DES engines and a shift-register architecture for doubling throughput. Lamport-Diffie-Merkle signatures can take advantage of massive parallelism, allowing over a 100 instances of PQSDES to run concurrently to complete the signing or verification of a signature.  (For applications requiring high speed data-privacy and integrity in hardware please see Synaptic Labs' VEST family of ciphers).

PQSDES can enable the full suite of high assurance cryptographic operations to be efficiently performed on smaller hardware devices than AES with RSA or ECC while maintaining a full breadth of support through to high-throughput hardware accelerated web-servers.

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