• "Some physicists predicted that within the next 10 to 20 years quantum computers will be built that are sufficiently powerful to implement Shor’s ideas and to break all existing public key schemes. Thus we need to look ahead to a future of quantum computers, and we need to prepare the cryptographic world for that future.

    Prof Seth Lloyd of MIT, MIT Review 2008

    Read more...
  • Build-in Security: Ensure that security is considered and built into the design of new infrastructure, so that our critical assets are protected from the start and more resilient to naturally-occurring and deliberate threats throughout their life-cycle."

    Obama-Biden Plan, Agenda: Homeland Security, December 2008

    Read more...
  • In the next five years we will counter many 'hacker' attacks but we will not be safe from Nation States and other large entities

    Brian Snow, Former Technical Director of the US National Security Agency (NSA), "We need assurance!", 1999-2008

    Read more...

Synaptic PQSAES cipher-hash Home

AES is the new software efficient block cipher standard by US NIST. New hardware devices are beginning to implement the new US NIST Advanced Encryption Standard.

Drawing from our experience with the design of the VEST hardware cipher Synaptic is completing the specifications of a family of enhanced modes-of-operation for AES that significantly increase its security margins, increase its key length up to 512-bits and enable it to perform collision resistant hash operations with message digests longer than SHA-512.

PQSAES was purpose built to enable Synaptic Labs' key exchange technologies and a range of Lamport-Diffie-Merkle digital signatures to run efficiently on area constrained hardware devices that have a 8-bit or larger CPU and a hardware dedicated AES coprocessor.

Lamport-Diffie-Merkle digital signatures are the next generation of digital signature technology set to replace the at-risk RSA and ECC. To achieve good performance Lamport-Diffie-Merkle signatures requires high-speed collision resistant hash functions. Unfortunately the industry standard SHA-1 and SHA-2 hash functions are very expensive to implement in hardware with the minimum SHA-256 implementation requiring 21K to 25K gates. Adding support for multiple versions of SHA also results in an increase in a much larger minimum circuit area 40K gates. For these reasons it is exceptionally rare to find SHA-256 implemented in area constrained hardware devices. PQSAES is designed to achieve high speed hash functions by taking advantage of hardware accelerated AES coprocessors.

In area constrained applications that have already have a small micro controller the addition of a 3k-6k gate AES coprocessor and PQSAES software enables the full suite of cryptographic operations including: key exchanges, 100 year secure single pass data privacy with message checking, collision resistant hashes and digital signatures. PQSAES with hardware AES acceleration is anticipated to achieve less power consumption than than equivalently rated operations performed using AES or SHA purely in software. PQSAES also supports a wide range of message digest lengths for cryptographic hash operations without an increase in circuit area. For these reasons PQSAES is excellent for ambient intelligence applications.

Unfortunately there are not a very large number of smart cards that support AES in hardware in production at this time. The smart card industry has previously standardised on the DES cipher to support the banking industry. If you require broad smart card support, or cryptographic systems with the widest range of interoperability, you might consider reviewing Synaptic Labs' PQSDES cipher.

In desktop environments PQSAES should achieve outstanding performance. AES is significantly faster than DES in general purpose software. PQSAES will enable 512-bit privacy operations with 512-bit message digests at approximately the same time it would take to perform the significantly weaker AES-256 privacy operations with AES-128 message digest operations.

In semiconductor applications the PQSAES cipher can be implemented with a wide range of circuit area / bandwidth trade-offs. In area constrained environments a very simple programmable finite state machine (Read, Write, XOR) can be coupled with a hardware AES module when a small micro controller is not available. In higher performance applications PQSAES can be implemented with two AES engines and a shift-register architecture for doubling throughput. Lamport-Diffie-Merkle signatures can take advantage of massive parallelism, allowing over a 100 instances of PQSAES to run concurrently to complete the signing or verification of a signature.  (For applications requiring high speed data-privacy and integrity in hardware please see Synaptic Labs' VEST family of ciphers).

PQSAES can enable the full suite of high assurance cryptographic operations to be efficiently performed on smaller hardware devices than (AES with RSA or ECC) while maintaining a full breadth of support through to high-throughput hardware accelerated web-servers.

Access to additional information in this category may be restricted from you.

Information available under this user account is accessible via the menu bar on the right of the screen under the PQSAES cipher-hash menu item.

Last Updated on Sunday, 04 January 2009 12:10
 
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