• “The time needed to factor an RSA integer is the same order as the time needed to use that same integer as modulus for a single RSA encryption.   In other words, it takes no more time to break RSA on a quantum computer (up to a multiplicative constant) than to use it legitimately on a classical computer.”

    Professor Gilles Brassard,  "Quantum Information Processing: The Good, the Bad and the Ugly", 1997

    Read more...

  • “In the next five years we will counter many 'hacker' attacks but we will not be safe from Nation States and other large entities”

    Brian Snow, Former Technical Director of the US National Security Agency (NSA), "We need assurance!", 1999-2008

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  • “When will we be secure? Nobody knows for sure – but it cannot happen before commercial security products and services possess not only enough functionality to satisfy customers’ stated needs, but also sufficient assurance of quality, reliability, safety, and appropriateness for use. Such assurances are lacking in most of today’s commercial security products and services.”

    Brian Snow, Former Technical Director of the US National Security Agency (NSA), "We need Assurance", 2005

    Read more...
Home Resources Synaptic publications Cryptographic white papers: VEST pub: VEST, AES, SHA Hardware Performance Survey (2005)
pub: VEST, AES, SHA Hardware Performance Survey (2005)
Tuesday, 01 November 2005 00:00
Full Title: A Presentation on VEST Hardware Performance, Chip Area Measurements, Power Consumption Estimates and Benchmarking in Relation to the AES, SHA-256 and SHA-512
Authors:

Benjamin Gittins, Howard A. Landman, Sean O'Neil and Ron Kelson
Organisation:

Synaptic Laboratories Limited
Date:

Nov, 2005
Keywords: implementation, stream ciphers, hash functions, authenticated encryption, message digest, message authentication code, fastest hardware cipher, AES, SHA-256, SHA-512, SHA-2, FPGA, ASIC
Pages: 42
Electronic Publication: PDF
Abstract:

The ECRYPT/eSTREAM organisers have required all submissions to be benchmarked against the Advanced Encryption Standard (AES) and where applicable, a secure trusted authentication mechanism. The goal is stated to be to identify those eSTREAM submissions that offer an advance over AES efficiency in any one or more benchmark dimensions.

In this paper, we respond to the eSTREAM requirement and offer a wide-sweeping multi-dimensional analysis and comparison between VEST and the hardware implementations of the AES, AES-HMAC and SHA-2 primitives.

This analysis clearly establishes VEST superiority over the AES, HMAC and SHA-2 primitives generally while direct comparisons between VEST and several of the best AES HMAC and SHA-2 implementations illustrates VEST superiority measuring in the hundreds of percent on several design dimensions or axis.
Quote:
See:
Citation:

Benjamin Gittins, Howard A. Landman, Sean O'Neil, Ron Kelson, "A Presentation on VEST Hardware Performance, Chip Area Measurements, Power Consumption Estimates and Benchmarking in Relation to the AES, SHA-256 and SHA-512", Synaptic Laboratories Limited, 2005.
Related work: pub: 20 Gb/s VEST-32 on 110nm LSI Rapidchip (2006)


Last Updated on Sunday, 23 October 2011 09:01