Eco-friendly technologies, with world first capabilities, for embedded computing projects

Welcome to the website of the ICT R&D company, Synaptic Laboratories Ltd.
We solve hard problems to empower innovation.

In 2009, Synaptic Labs CTO was selected to participate at the White House's “closed, by invitation only” National Cybersecurity Summit (NITRD NCLY 2009).   He was was probably the only invitee from a company not based in Northern America.

The Summit proceedings published 6 proposals that were based on ~10 years of cross-domain foundational research by Synaptic Labs.    Those proposals were parts of Synaptic Labs' roadmap to enable a gradual and commercially viable shift towards a much safer and more secure computing and communications ecosystem (illustrated above).   

This ecosystem approach is based on innovative technology building blocks that solve hard problems.   These building blocks were designed after wide cross-domain research to ensure they are generally universal and re-usable across multiple industries and applications.   For example in the tiniest Internet of Things (IoT) projects, the most secure cloud computing systems, robust enterprise desktop computing and the highest assurance safety-critical applications, all with global scalability.   To be clear, this means each technology building block was designed to empower products developed by third parties, so that we can all take steps towards a safer ecosystem. 

Synaptic Labs differentiates itself from most other R&D companies by comprehensively addressing hard to very hard safety and security design problems, from the onset.   Since the Summit, Synaptic Labs has continued to consult widely with collaborating experts to identify needs and validate our solutions.   

Our universal building blocks (components) have been systematically advanced and developed to prove our claims, so they can be employed in projects to make this better ecosystem a reality.   Most importantly, each technology component achieves commercial viability by reducing costs while adding new capabilities that clearly increase the potential for innovation.   In this way a gradual (global) shift towards more robust, trustworthy and dependable computing and communication devices becomes possible.  

For example, our embedded memory management technologies (eMMU) for real-time applications remove the problems in existing MMU's such as lack of determinism.   They are also simpler, easier to certify, higher performance, more than 10 times smaller, with lower power consumption.   These are universally attractive features for any (safety critical and mixed-criticality) project.    Our real-time eMMU is viable in every chip, including IoT and tiny microcontroller applications (e.g. automotive).   They deliver the beneficial functionality of a true MMU, and more, with none of the downsides and limitations of conventional MMU's that force some industries such as automotive to employ MPU's.

We employ our technology building blocks in our own unique architecture designs.  For example in our high performance, industry and vendor neutral, cache-coherent shared-memory multi bus-master computer architectures.   These architectures are designed to enable multi-cores to be safely employed in high-criticality certified applications.  They can also be readily adapted for use by multiple processor vendors to extend their product offerings. 

To establish the competitive position of Synaptic Labs multi bus-master computer architecture designs, in 2014 we completed a comprehensive technical comparative analysis of the leading important R&D projects in this field.   All were measured against a list of ~180 to ~200 capabilities and requirements for a comprehensive and commercially viable solution.   Synaptic Labs's multi bus-master computer architectures address all ~200 requirements and capabilities, with the nearest competing research project addressing less than half.   Please contact us so we can assist you to identify the subset of these ~200 capabilities that will viably remove problems and open up the opportunities for innovation in your project.   

We welcome your enquiry.

Synaptic Labs' CTO (Benjamin Gittins) can be contacted by land line: +356 2701 9390, mobile: +356 9944 9390 or Skype during business hours (CET, UTC+1).   Alternatively, propose a date and time to talk by email.

So, today, Synaptic Labs offers comprehensive designs to overcome large complex innovation barriers.   We also offer components (building blocks) from those designs that are relatively simple standalone technologies that can be rapidly employed in existing projects, now.    We have carefully considered the real-world requirements of each component before implementation.   Your project can benefit from our years of completed cross-domain research. 

Our solutions therefore offer new capabilities that software and hardware project designers want, to make their projects easier, more open to innovation, more efficient, with lower cost to design and if necessary certify.   This includes solutions to the most demanding requirements of systems that face serious challenges.   Challenges such as increasing complexity, pressures for higher performance with lower power and reduced costs, and increasing safety and security demands in evolving industrial, avionics and defence standards.

Collectively, Synaptic Labs portfolio of high performance computing technologies are characterised as fast, efficient, vendor neutral, cross domain solutions, that enable superior to far-superior software performance on multiple axis, coupled with a significant reduction in total project development effort.

Some of our technologies are designed to empower innovation in general purpose (low-assurance, non real-time, uncertified) applications.   Many are specifically designed for, and to significantly reduce the development cost of, high-assurance real-time certified hardware and software applications.   All our designs are elegant.

On this page we will now introduce our unique and innovative memory management and cache subsystems.   They are 'stand-alone' solutions that can be employed alone or together, in your existing projects, today. 

They are suitable for single core, dual core, multi-core and many core projects in FPGA and ASIC. 

They are also foundational components within our own “Safe and Secure Real-Time” (SSRT) family of computing platforms.

The SSRT family of technologies, and their various subsystems (including the cache and memory management technologies), are
all designed so that they can be implemented to meet the current and future demanding requirements of automotive (AUTOSAR 2.0, ISO 26262,...), avionics (DO-178C, DO-254, CAST-32, ARINC-653,
DO-297/IMA, FACE 2.1, SKPP, ...), industrial control (IEC 61508, ...) as well as other price-sensitive embedded markets, such as mobile devices and the Internet of Things.

These unique hardware technologies enable more innovation in your project at lower effort and cost, because we have solved hard problems and eliminated serious costly constraints.   They will consistently enable lower power consumption per unit of work performed, and lower manufacturing costs, with improved safety and security.   Unique capabilities that will differentiate your project and increase your competitive edge.

There is more information below about our unique memory management and cache solutions.   

Due to commercial and IP constraints, this website cannot disclose the full extent of the capabilities in our technologies.   Please contact us to learn more about the true extent of our capabilities, and to explore how your own project can specifically benefit.  


Various foundational components of Synaptic Labs'
Safe and Secure Real-time (SSRT) Computing
family have been successfully prototyped.

Safe and Secure Real-time Computing

Introducing our unique and innovative memory management technologies

With their best in class performance capabilities on every axis, our family of tiny embedded Memory Management Units (eMMU) are positioned to make all existing Memory Management Units (MMU’s) and Memory Protection Units (MPU’s) obsolete.

New design projects can now select a variant of the eMMU family to match their operating system and project objectives in all embedded applications, including those employing high-assurance RTOS through to the feature rich Linux operating systems.

The eMMU are currently optimised for 32-bit embedded systems, but can be readily adapted for use in 8-bit, 16-bit, and 64-bit embedded applications.

embedded Memory Management Unit Being physically tiny, they are viable in very resource constrained projects that previously would have been forced to employ either (a) inferior MPU controls, or (b) no memory management controls at all!   All benefits can be won even when deployed in the soft logic of small FPGA's.

More introductory information is provided further below. 
Specific details are available upon request.
We welcome your enquiry.

Introducing our portfolio of unique and innovative cache solutions

Synaptic Labs is aggressively pursuing the world’s most advanced cache solutions for high-assurance, safety-critical, and real-time applications.

Like all of the technologies in Synaptic Labs’ “Safe and Secure Real-Time” (SSRT) family, our cache designs are well positioned to address the most demanding safety and security requirements of multiple industries with exceptional performance.   This includes the automotive, industrial control and avionics industries.

Synaptic Labs offers three classes of time-analysable caches:

  1. Real-time caches with coherency for use in very high-bandwidth on-chip shared SRAM applications.
  2. Real-time caches with coherency for use with shared off-chip SDRAM memory.
  3. Real-time caches with no coherency for use with private off-chip SDRAM memory.

All three classes of cache solution are carefully designed to achieve best-of-class performance within their specific use case, whether implemented in the programmable logic of FPGA or in ASIC.

Synaptic Labs’ "caches with coherency" are the only known designs in the world that achieve scalable coherency over 8 or more cores, with high throughput and zero timing jitter.

All our caches are designed to address the “unknown effective data address problem”, a problem which can effectively eliminate most of the performance gains of various commercial cache designs for many types of tasks running in real-time systems.

Our caches are carefully designed to perform fast flushing.   This capability being absolutely required to support the effective use of cache in robust time and space partitioning environments.

Our caches are also designed to run efficiently with high throughput when implemented in the programmable logic of SRAM based FPGA.

The broad range of innovations and careful design decisions present in our real-time caches will make the use of other caches (as found in 3rd party ASIC and FPGA processors) obsolete in high-criticality systems.

Specific technical details are available upon request.
We welcome your enquiry.

More detailed information on our unique and innovative embedded memory management units (eMMU)
Tiny, fast, efficient, vendor neutral solutions for both high-assurance RTOS and Linux environments.

Embedded MMU for Real-Time (eMMU-for-RT)   

The eMMU-for-RT technology is simply the best choice for any RTOS based embedded project considering an MPU or MMU based memory management solution.

The tiny eMMU-for-RT is the first true MMU that explicitly addresses the most demanding requirements of high-criticality safety, security and/or real-time systems.   By doing so, it can significantly lower your costs for certification and future re-certification of real-time tasks.

The eMMU-for-RT delivers superior to far superior performance in a tiny fraction of the circuit area, power and complexity of existing MMU and multi-region MPU (see comparisons in the charts to the right).

In fact, the performance profile of the eMMU-for-RT eliminates all arguments in support of the less-capable MPU technologies.   It also uniquely eliminates all arguments that apply against the use of (conventional) MMU technologies (in favour of MPU’s) in high criticality and automotive systems.   Technical details are available upon request.

The low design complexity of the eMMU-for-RT is reasonably expected to reduce the high-assurance development costs of coupling an MMU to a core by up to 50%.   Furthermore, the simplicity of the architecture permits reduced cost when porting high-assurance RTOS to computing platforms that employ eMMU-for-RT.

Embedded MMU for Non Real-Time (eMMU-for-NRT)   

eMMU-for-NRT is the world's smallest, lowest power, high-performance MMU design optimised for general purpose applications (non real-time).   eMMU-for-NRT is perfect for high-performance embedded Linux, GENEVI and Android applications.

The tiny circuit area and lower power budget of the eMMU-for-NRT makes it well suited to replace the relatively large MMU found in today’s FPGA and ASIC designs in non real-time applications.

eMMU supports mixed criticality applications   

Synaptic Labs' offers eMMU solutions optimised for mixed criticality applications mixing RT and NRT requirements.  Please contact us to learn more.

More about the ground breaking eMMU family of technologies can be found below.  

Compared to a conventional MMU eMMU-RT eMMU-NRT
Combinatorial logic area >10x less Far smaller
Best case throughput As fast As fast
Worst case throughput Much higher Faster
Context swapping performance Much higher Much higher
Determinism Much better Comparable
Ease of programming Much easier Comparable
Ease of real-time sw certification Much easier Comparable

Compared to a conventional MPU
(MPU offer less functionality than MMU)
Combinatorial logic area >5x less Far smaller
Overall functional capabilities Superior Superior
Best case throughput As fast As fast
Worst case throughput As fast Less
Context swapping performance As fast As fast
Determinism Similar Less
Ease of programming Comparable Harder
Ease of real-time sw certification Comparable Harder

Large number of protection regions No Yes Yes Yes
Address space translation capabilities No Yes Yes Yes
Suitable for high-end RTOS No Yes  Yes  Yes 
Suitable for Linux No Yes Optional Yes
Ideal for real-time tasks Yes No Yes No
Ideal for task context swapping  Yes No Yes Yes
Relative level memory consumption Low High Low High
Increase in logic element resources over fast NIOSII / MicroBlaze soft cores ~33% ~66% < 6% Low

Lets talk!

As mentioned above, due to commercial and IP constraints, we do not disclose the full extent of the capabilities of our technologies publicly on this website.  Please contact us to learn more about the true-extent of our capabilities, and to explore how your own project can specifically benefit.

Synaptic Labs' CTO (Benjamin Gittins) can be contacted by land line: +356 2701 9390, mobile: +356 9944 9390 or Skype during business hours (CET, UTC+1).   Alternatively, propose a date and time to talk by email.

What is an MPU?

A memory protection unit (MPU) sits between the processor core and the memory subsystem (such as SRAM or SDRAM).

An MPU checks the permission of each memory request issued by the currently active task running on a processor core.

Most commercial MPU offer from 4 to 32 concurrent protection regions.   Each memory transfer request is checked against the active protection regions.

When the currently active user task changes to a different user task, the MPU is reprogrammed to use a new set of protection regions as required for that incoming user task.

What is an MMU?

Similar to an MPU, a memory management unit (MMU) checks the permission of every memory transfer request issued by a processor core.

In addition, the MMU is responsible for translating the "virtual address" of each memory transfer request to a corresponding "physical address".   This capability permits each task to have its own virtual (private, independent) view of memory.   This virtualisation capability is then used to isolate the development, testing and (where required) certification of each task.

When the currently active user task changes to a different user task, the MMU is reprogrammed with a new set of address translation tables as required for that incoming user task.

Conventional MMU suffer from real-time design flaws.   Those real-time design flaws make conventional MMU harder (and thus more expensive) to employ correctly in real-time and safety critical applications.

What is an eMMU?

The eMMU is a new class of tiny MMU optimised for use in embedded systems. All eMMU are true MMU in that they perform both permission checking and memory address translation.

The eMMU-for-RT boasts a revolutionary new type of architecture that has been optimised to meet the most demanding performance and safety requirements of high assurance real-time applications and high assurance real-time operating systems (RTOS).   The eMMU-for-RT is unique in that it explicitly addresses the real-time design flaws that are present in all conventional MMU architectures.

The eMMU-for-NRT boasts an evolutionary new type of architecture that delivers superior memory management performance with extremely low resource requirements.   The eMMU-for-NRT is designed to support general purpose operating systems (GPOS), such as Linux, in all embedded applications.

Both the eMMU-for-RT and eMMU-for-NRT are designed to optimise the performance of the system when the currently active user task changes to a different user task.

Why MPU's were used

In safety critical applications, an MPU (or MMU) is used to protect the instructions and data of safety critical tasks from unauthorised read and/or write access by lower criticality tasks.   For example, the AUTOSAR automotive software architecture requires either an MPU or MMU to ensure high-criticality tasks are not corrupted by other tasks.

This isolation capability is important because lower criticality tasks are typically developed at a lower cost (and with less testing) than high criticality tasks.   This means low-criticality tasks are far more likely to have software bugs (implementation flaws) that could corrupt the code and/or data of other tasks.

Many industries (including automotive) were forced to select an MPU (with its reduced functionality) over a conventional MMU for several reasons, including significant reductions in manufacturing costs, and a significant increase in determinism.

Synaptic Labs' eMMU-for-RT removes those reasons to employ an MPU, and permits those industries to transition to a true MMU with comparable to far less cost than an MPU.

Why MMU's were used

Today's high-assurance automotive and avionics real-time operating systems all require a memory management unit (MMU) in the hardware.   The known limitations in conventional MMU had to be managed at an increased cost over the use of an MPU.

The "virtualisation" capabilities enabled by an MMU permit high-assurance RTOS to robustly isolate tasks.   Each task can then be tested and certified in complete isolation.   This can result in a significant increase in safety and productivity along with a significant reduction in testing and certification costs.   Certification artefacts could be re-used more easily between projects.

Unfortunately, the timing jitter introduced by a conventional MMU makes it much harder to correctly establish the worst-case performance of real-time tasks to ensure that they meet their deadlines.   This complexity leads to increased project and software certification costs.

In high-criticality applications, Synaptic Labs' eMMU-for-RT provides true MMU capabilities with far less jitter (i.e. far higher determinism) and far less cost than any conventional MMU.   Exact details available upon request.

General purpose operating systems (Linux, Android, GENEVI) typically rely on the presence of an MMU to manage the complexity of the applications running on them.   MMU’s are often employed to reduce the probability of one task crashing the entire computer.   Synaptic Labs’ eMMU-for-NRT delivers all the capabilities required by general purpose operating systems with superior performance and far lower cost than any conventional MMU.

Why an eMMU is better!

The tiny eMMU-for-RT provides the MMU capabilities required by high-assurance RTOS in far less circuit area than today's MMU (>10x less) or multi-region MPU (>5x less) without sacrificing determinism.   This permits the use of a true MMU in any application that was previously forced to use an MPU, and this supports the wider use of high assurance RTOS for greater safety and security, which is the trend in many industries.

Advantageously, this significant reduction in circuit area also correlates to a reduced level of exposure to radiation effects (SET, SEU, MBU) in aerospace and terrestrial applications, making the eMMU-for-RT inherently safer to use.   The inherent simplicity and relatively high clock-speed of the eMMU-for-RT permits additional fault tolerance controls to be cost effectively applied to further increase safety.

The level of determinism present in the eMMU-for-RT will allow far easier certification of real-time software than conventional MMU architectures, while achieving superior to far superior performance.

Furthermore, the eMMU-for-RT hardware is easier for core vendors to implement (and certify) than conventional MMU architectures.

As previously stated, the eMMU-for-NRT provides the MMU capabilities required by general-purpose operating systems in less circuit area, with higher performance and lower power than today's conventional MMU, making it the ideal choice for embedded Linux, GENEVI and Android applications.

All members of the eMMU family also offer far superior address space context swapping / task swapping performance than a conventional MMU, leading to potentially significant gains in performance.

See the comparative tables above and to the right hand side of this page for more examples of why it’s always better to employ an eMMU.   Further exact details are available upon request.

We are ready to explore the application and superior benefits of an eMMU, and/or our real-time cache technologies, and/or our “Safe and Secure Real-Time” (SSRT) family of computing platforms in your project!

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Synaptic Laboratories Limited: Technologies For A Safe and Secure High Performance Computing and Communications Ecosystem.